DDR3 SDRAM

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H5TQ4G63MFR

The H5TQ4G43MFR-xxC, H5TQ4G83MFR-xxC and H5TQ4G63MFR-xxC are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Features

  • VDD=VDDQ=1.5V +/- 0.075V
  • Fully differential clock inputs (CK, /CK) operation
  • Differential Data Strobe (DQS, /DQS)
  • On chip DLL align DQ, DQS and /DQS transition with CK transition
  • DM masks write data-in at the both rising and falling edges of the data strobe
  • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
  • Programmable CAS latency 5, 6, 7, 8, 9, 10 and 11, 13 supported
  • Programmable additive latency 0, CL-1, and CL-2 supported
  • Programmable CAS Write latency (CWL) = 5, 6, 7, 8
  • Programmable burst length 4/8 with both nibble sequential and interleave mode
  • BL switch on the fly
  • 8banks
  • Average Refresh Cycle (Tcase of 0 oC~ 95oC)
    - 7.8 µs at 0oC ~ 85 oC
    - 3.9 µs at 85oC ~ 95 oC
  • Auto Self Refresh supported
  • JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA (x16)
  • Driver strength selected by EMRS
  • Dynamic On Die Termination supported
  • Asynchronous RESET pin supported
  • ZQ calibration supported
  • TDQS (Termination Data Strobe) supported (x8 only)
  • Write Levelization supported
  • 8 bit pre-fetch
  • This product in compliance with the RoHS directive.

Technical Data Sheet

Technical Data Sheet
Part Number Rev. Update Date Remark
H5TQ4G63MFR 1.0 2012-11-07  

Simulation Model

Simulation Model
Part Number Rev. Update Date Remark
IBIS 1.1 2011-11-22  
Verilog 1.95 2012-09-24  
HSpice 1.1 2012-06-04  

Device Operation

Device Operation
File Name Update Date Remark
DDR3_Device_operation_timing_diagram_computing.pdf 2013-10-24  

Ordering Information


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