The H5TC(Q)4G63CFR-xxC are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the graphics applications which require large memory density and high bandwidth and low power operation. 1.35v speed part provides backward compatibility with the 1.5V DDR3. SK hynix 4Gb DDR3 SDRAM offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.


• DQ Power & Power supply:

  VDD=VDDQ=1.35V + 0.100 / - 0.065V

  VDD=VDDQ=1.5V +/- 0.075V

• Fully differential clock inputs (CK, CK) operation

• Differential Data Strobe (DQS, DQS)

• On chip DLL align DQ, DQS and DQS transition with CK transition

• DM masks write data-in at the both rising and falling edges of the data strobe

• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock

• Programmable CAS latency 5, 6, 7, 8, 9, 10,11,12,13, 14 and 15 supported

• Programmable additive latency 0, CL-1, and CL-2 supported

• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10 and 11

• Programmable burst length 4/8 with both nibble sequential and interleave mode

• BL switch on the fly

• 8banks

• 8K refresh cycles/64ms

• Auto Self Refresh supported

• JEDEC standard 96ball FBGA (x16)

• Driver strength selected by EMRS

• Dynamic On Die Termination supported

• Asynchronous RESET pin supported

• ZQ calibration supported

• Write Levelization supported

• 8 bit pre-fetch


SpeedSpeed의 Part Number, Speed를 나타낸 표 입니다.
Part Number Speed
N2 1.2GHz
N0 1.0GHz