PRODUCTSDDR3 SDRAM

H5TQ8G83AMR

The H5TQ8G43AMR-xxC, H5TQ8G83AMR-xxC and H5TQ8G63AMR-xxC are a 8Gb normal power Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth and normal power operation at 1.5V.
SK hynix 8Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Features

  •  VDD=VDDQ=1.5V +/- 0.075V
  • Fully differential clock inputs (CK, CK#) operation
  • Differential Data Strobe (DQS, DQS#)
  • On chip DLL align DQ, DQS and DQS# transition with CK transition
  • DM masks write data-in at the both rising and falling edges of the data strobe
  • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
  • Programmable CAS latency 5, 6, 7, 8, 9, 10, 11 and 13 supported
  • Programmable additive latency 0, CL-1, and CL-2 supported
  • Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10
  • Programmable burst length 4/8 with both nibble equential and interleave mode
  • BL switch on the fly
  • 8banks
  • Average Refresh Cycle   (Tcase of 0oC~95oC)  
    - 7.8 µs at 0oC ~ 85 oC                                                                
    - 3.9 µs at 85oC ~ 95 oC
  • JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16)
  • Driver strength selected by EMRS
  • Dynamic On Die Termination supported
  • Asynchronous RESET pin supported
  • ZQ calibration supported
  • TDQS (Termination Data Strobe) supported (x8 only)
  • Write Levelization supported
  • 8 bit pre-fetch
  • This product in compliance with the RoHS directive.

Technical Data Sheet

Technical Data Sheet Technical Data Sheet의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
H5TQ8G83AMR 1.0 2013-12-05  

Simulation Model

Simulation Model Simulation Model의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
IBIS 1.5 2014-05-27  
Verilog 1.95 2013-08-01  
HSpice 1.2 2013-08-01  

Device Operation

Device Operation Device Operation의 Part File Name, Update Date, Remark를 나타낸 표 입니다
Part Number Update Date Remark
DDR3_Device_operation_timing_diagram_computing.pdf 2013-10-24  

Speed

SpeedSpeed의 Part Number, Speed를 나타낸 표 입니다.
Part Number Speed
G7 1066 7-7-7
H9 1333 9-9-9
PB 1600 11-11-11
RD 1866 13-13-13