The GDDR6 SGRAM is a high-speed dynamic random-access memory designed for applications requiring high bandwidth. GDDR6 devices contain the following number of bits:

8 Gb has 8,589,934,592 bits

The GDDR6 SGRAM’s high-speed interface is optimized for point-to-point connections to a host controller. On-die termination (ODT) is provided for all high-speed interface signals to eliminate the need for termination resistors in the system.
GDDR6 uses a 16n prefetch architecture and a DDR interface to achieve high-speed operation. The device’s architecture consists of two 16 bit wide fully independent channels.
GDDR6 operates from a differential clock CK_t and CK_c. CK is common to both channels. Command and Address (CA) are registered at every rising edge of CK and every falling edge of CK. There are both single cycle and multi cycle commands. See command truth table for details.
GDDR6 uses a free running differential forwarded clock (WCK_t/WCK_c) with both input and output data registered and driven respectively at both edges of the forwarded WCK. See Clocking section for details.
Read and write accesses to GDDR6 are burst oriented; accesses start at a selected location and consists of a total of sixteen data words. Accesses begin with the registration of an Activate command, which is then followed by a Read, Write (WOM) or masked Write (WDM, WSM) command.
The row and bank address to be accessed is registered coincident with the Activate command. The address bits registered coincident with the Read, Write or masked Write command are used to select the bank and the starting column location for the burst access.
This specification includes all features and functionality required for GDDR6 SGRAM devices. In many cases the GDDR6 specification describes the behavior of a single channel.


•2 separate independent channels with point-to-point interface for data, address and command

•Half CA data rate differential clock inputs CK_t/CK_c for CMD/ADD (CA) per 2 channels

•Four half data rate differential clock inputs WCK_t/WCK_c, each associated with a data byte (DQ, DBI_n, EDC) in the channel•Double Data Rate (DDR) data (with regards to the WCK)

•Double Data Rate (DDR) Command Address (with regards to the CK)

•16 internal banks

•4 bank groups for tCCDL = 3 tCK and 4 tCK

•16n prefetch architecture: 256 bit per array read or write access per channel

•Burst length: 16 only

•Programmable READ latency: 9 to 27 tCK

•Programmable WRITE latency: 5 to 7 tCK

•WRITE Data mask function via CA bus (single/double byte mask)

•Data bus inversion (DBI) & Command Address bus inversion (CABI)

•Command Address training: command address input monitoring by DQ/DBI_n/EDC signals

•WCK2CK clock training with phase information by EDC signals

•Data read and write training via READ FIFO (depth 6)

•READ FIFO pattern preload by LDFF command

•Direct write data load to READ FIFO by WRTR command

•Consecutive read of READ FIFO by RDTR command

•Read/Write data transmission integrity secured by cyclic redundancy check using either a half or full data rate CRC

•READ/WRITE EDC on/off mode

•Programmable EDC hold pattern for CDR

•Programmable CRC READ latency = 1 to 4 tCK and CRC WRITE latency = 10 to 14 tCK•Low Power modes

•On-chip temperature sensor with read-out

•Auto precharge option for each burst access

•Auto refresh & self refresh modes

•32ms, auto refresh (16k cycles)

•Temperature sensor controlled self refresh rate and Partial Array Self Refresh

•Per-Bank / Per-2-Bank Refresh

•Optional digital tRAS lockout

•On-die termination (ODT)

•ODT and output driver strength auto-calibration with external resistor ZQ

•Programmable termination and driver strength offsets (40 ohm to 60ohm)•Internal VREF for data inputs and CA inputs with programmable levels

•Separate internal VREF for CA (Command / Address) inputs

•Vendor ID1 and ID2 for identification

•x16/x8 mode configuration set at power-up with EDC

•Pseudo-channel mode (PC mode) configuration set at power up with CA6

•1.35V +/- 0.0405V supply for device operation (VDD)

•1.35V +/- 0.0405V supply for I/O interface (VDDQ)

•1.8 + 0.108V / - 0.054V supply for VPP

•180 ball BGA package with 0.75mm pitch


SpeedSpeed의 Part Number, Voltage, Speed를 나타낸 표 입니다.
Part Number Speed Voltage
S2 6.0GHz/7.0GHz 1.8V/1.35V/13.5V
S0 5.0GHz/6.0GHz 1.8V/1.35V/13.5V