· VDD1 = 1.8V (1.7V to 1.95V)
· VDD2 and VDDCA = 1.1V (1.06V to 1.17V)
· VDDQ = 0.6V (0.57V to 0.65V)
· VSSQ terminated DQ signals (DQ, DQS_t, DQS_c, DMI)
· Single data rate architecture for command and address;
  - all control and address latched at rising edge of the clock
· Double data rate architecture for data Bus;
  - two data accesses per clock cycle
· Differential clock inputs (CK_t, CK_c)
· Bi-directional differential data strobe (DQS_t, DQS_c)
  - Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c)
· DMI pin support for write data masking and DBIdc functionality
· Programmable RL (Read Latency) and WL (Write Latency)
· Burst length: 16 (default), 32 and On-the-fly
  - On the fly mode is enabled by MRS
· Auto refresh and self refresh supported
· All bank auto refresh and directed per bank auto refresh supported
· Auto TCSR (Temperature Compensated Self Refresh)
· PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask
· Background ZQ Calibration


SpeedSpeed의 Part Number, Speed를 나타낸 표 입니다.
Part Number Speed
L 3200Mbps
M 3733Mbps