The H5TC2G83GFR-xxA(I,L,J) and H5TC2G63GFR-xxA(I,L,J) are a 2Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. SK Hynix 2Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While
all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.


• VDD=VDDQ=1.35V + 0.100 / - 0.067V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on therising edges of the clock
• Programmable CAS latency 6, 7, 8, 9, 10, 11, 12 and 13 supported
• Programmable additive latency 0, CL-1, and CL-2 supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8 and 9
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• BL switch on the fly
• 8banks
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
  - 7.8 μs at 0oC ~ 85 oC
  - 3.9 μs at 85oC ~ 95 oC
  Commerical Temperature (0oC ~ 95 oC)
  Industrial Temperature(-40oC ~ 95 oC)
• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch

Technical Data Sheet

Technical Data Sheet Technical Data Sheet의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
H5TC2G83GFR 1.3 2015-11-06  

Simulation Model

Simulation Model Simulation Model의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
Verilog 1.31 2012-09-24  
HSpice 1.1 2015-09-24  
IBIS 1.0 2015-07-20  
IBIS 1.0 2015-07-20  -xxI


SpeedSpeed의 Part Number, Speed를 나타낸 표 입니다.
Part Number Speed
G7 1066 7-7-7
H9 1333 9-9-9
PB 1600 11-11-11
RD 1866 13-13-13