The SK Hynix HY5V26F(L)F(P)-x(I) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth.
HY5V26F(L)F(P)-x(I) series is organized as 4banks of 2,097,152 x 16.
HY5V26E(L)F(P)-x(I) is offering fully synchronous operation referenced to a positive edge of the clock.
All inputs andoutputs are synchronized with the rising edge of the clock input.
The data paths are internally pipelined to achieve very high bandwidth.
All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave).
A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-stricted by a '2N' rule)
- Voltage: VDD and VDDQ 3.3V supply voltage
- All device pins are compatible with LVTTL interface
- 54 Ball FBGA (Lead or Lead Free Package)
- All inputs and outputs referenced to positive edge of system clock
- Data mask function by UDQM, LDQM
- Internal four banks operation
- Auto refresh and self refresh
- 4096 Refresh cycles / 64ms
- Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
- Programmable CAS Latency; 2, 3 Clocks
- Burst Read Single Write operation
- Operation temperature
- HY5V26F(L)F(P)-XX Series: 0 ~ 70oC
- HY5V26F(L)F(P)-X(I) Series: -40 ~ 85oC
This product is in compliance with the directive pertaining of RoHS.
Technical Data Sheet
|Part Number||Rev.||Update Date||Remark|