PRODUCTSSDR SDRAM

HY57V281620HCT

The SK Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applicationswhich require large memory density and high bandwidth. HY57V281620HC(L/S)T is organized as 4banks of 2,097,152x16.

HY57V281620HC(L/S)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs aresynchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All inputand output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiatedby a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst ofread or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burstread or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

Features

  • Single 3.3±0.3V power supply
  • All device pins are compatible with LVTTL interface
  • JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
  • All inputs and outputs referenced to positive edge of system clock
  • Data mask function by UDQM or LDQM
  • Internal four banks operation
  • Auto refresh and self refresh
  • 4096 refresh cycles / 64ms
  • Programmable Burst Length and Burst Type
    • 1, 2, 4, 8 or Full page for Sequential Burst
    • 1, 2, 4 or 8 for Interleave Burst
  • Programmable CAS Latency ; 2, 3 Clocks

Technical Data Sheet

Technical Data Sheet Technical Data Sheet의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
HY57V281620HCT 0.3 2004-04-19  
HY57V281620HCTP 0.1 2004-04-19  Lead Free
HY57V281620HCT-xI 1.0 2004-04-19  Industrial

Speed

SpeedSpeed의 Part Number, Speed를 나타낸 표 입니다.
Part Number Speed
6 166MHz
7 143MHz
K 266A
H 266B
8 125MHz
P PC100,CL2
S PC100,CL3