The H5TQ1G6(8)3DFR-xxx series are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
SK Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.


  • DQ Power & Power supply : VDD & VDDQ = 1.5V +/- 0.075V
  • DQ Ground supply : VSSQ = Ground
  • Fully differential clock inputs (CK, /CK) operation
  • Differential Data Strobe (DQS, /DQS)
  • On chip DLL align DQ, DQS and /DQS transition with CK transition
  • DM masks write data-in at the both rising and falling edges of the data strobe
  • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
  • Programmable CAS latency 6, 7, 8, 9, 10, and 11supported
  • Programmable additive latency 0, CL-1, and CL-2 supported
  • Programmable CAS Write latency (CWL) = 5, 6, 7, 8
  • Programmable burst length 4/8 with both nibble sequential and interleave mode
  • Programmable PASR(Partial Array Self-Refresh) for Digital consumer Applications.
  • Programmable BL=4 supported (tCCD=2CLK) for Digi-tal consumer Applications.
  • Programmable ZQ calibration supported
  • BL switch on the fly
  • 8banks
  • Average Refresh Cycle (Tcase of 0 °C~ 95 °C)
    - 7.8 µs at -40°C ~ 85 °C
    - 3.9 µs at 85°C ~ 95 °C
    Commercial Temperature ( 0°C ~ 85 °C)
    Industrial Temperature ( -40°C ~ 95 °C)
  • JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
  • Driver strength selected by EMRS
  • Dynamic On Die Termination supported
  • Asynchronous RESET pin supported
  • TDQS (Termination Data Strobe) supported (x8 only)
  • This product in compliance with the RoHS directive.

Technical Data Sheet

Technical Data Sheet Technical Data Sheet의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
H5TQ1G63DFR 1.8 2013-06-28  temp. : C, I

Simulation Model

Simulation Model Simulation Model의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
IBIS 1.4 2010-12-16  H5TQ1G63DFR
IBIS 1.0 2012-07-03  H5TQ1G63DFR-xI
Verilog 1.9 2011-10-31  
HSpice 1.2 2011-10-31  


SpeedSpeed의 Part Number, Speed를 나타낸 표 입니다.
Part Number Speed
G7 1066 7-7-7
H9 1333 9-9-9
PB 1600 11-11-11
RD 1866 13-13-13
TE 2133 14-14-14