PRODUCTSDDR2 SDRAM

H5PS1G63JFR

Features

  • VDD = 1.8 +/- 0.1V
  • VDDQ = 1.8 +/- 0.1V
  • All inputs and outputs are compatible with SSTL_18 interface
  • 8 banks
  • Fully differential clock inputs (CK, /CK) operation
  • Double data rate interface
  • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, /DQS)
  • Differential Data Strobe (DQS, /DQS)
  • Data outputs on DQS, /DQS edges when read (edged DQ)
  • Data inputs on DQS centers when write (centered DQ)
  • On chip DLL align DQ, DQS and /DQS transition with CK transition
  • DM mask write data-in at the both rising and falling edges of the data strobe
  • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
  • Programmable CAS latency 3, 4, 5 and 6 supported
  • Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
  • Programmable burst length 4/8 with both nibble sequential and interleave mode
  • Internal eight bank operations with single pulsed RAS
  • Auto refresh and self refresh supported
  • tRAS lockout supported
  • 8K refresh cycles /64ms
  • JEDEC standard 84ball FBGA(x16)
  • Full strength driver option controlled by EMR
  • On Die Termination supported
  • Off Chip Driver Impedance Adjustment supported
  • Self-Refresh High Temperature Entry

Technical Data Sheet

Technical Data Sheet Technical Data Sheet의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
H5PS1G63JFR 2.0 2014-03-20  

Simulation Model

Simulation Model Simulation Model의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
IBIS 1.1 2011-10-26  
Verilog 1.0 2011-10-26  
HSpice 1.0 2012-03-29  

Speed

SpeedSpeed의 Part Number, Speed를 나타낸 표 입니다.
Part Number Speed
E3 400 3-3-3
C4 533 4-4-4
Y5 667 5-5-5
S6 800 6-6-6
S5 800 5-5-5
G7 1066 7-7-7