Overview
In recent years, interest in DRAM has surged alongside High Bandwidth Memory (HBM), Compute Express Link (CXL), and Processing-in-Memory (PIM). Academic research increasingly explores DRAM architecture to support these emerging use cases, yet the rapid pace of product innovation makes it challenging to stay aligned with commercial developments.
This tutorial aims to bridge that gap. We provide an up-to-date view of DRAM standardization trends and commercialization status, outline challenges observed in real deployments, and highlight research opportunities where academia–industry collaboration can move the field forward.
Schedule
Each session comprises 30min tutorial and 5min QnA
- Location: Berkeley (Lotte Hotel, 36F)
- 08:20~, Opening
- 08:30~, HBM4
- 09:05~, DDR5
- 09:40~, LPDDR6
- 10:15~, Break
- 10:30~, CXL
- 11:05~, PIM
Sessions & Abstracts
HBM4 — Evolution & What’s Next Speaker: Kijoon Chang
A guided tour through HBM generations with a focus on HBM4. We will highlight key spec changes relevant to microarchitecture researchers, then discuss where the next generation HBM may head and the challenges ahead for runtimes, packaging, and systems.
DDR5 — Server CPU Workloads and DIMM choice Speaker: Dongha Jung
While GPUs paired with HBM often dominate AI discussions, server CPUs and DDR5 remain vital to sustaining and optimizing the AI data pipeline. In this session, we will begin with a clear overview of DDR5—the leading server DIMM standard—then examine how to select the most effective DIMM options for different workloads, supported by benchmarking results. We will also introduce newly added features that enhance RowHammer mitigation.
LPDDR6 — From LPDDR5 to LPDDR6 Speaker: Jino Choi
An in-depth overview of the transition from LPDDR5 to LPDDR6: architectural innovations, feature additions, and how higher data rates are achieved while preserving the low-power envelope required for mobile and AI-edge applications. The session will also cover development challenges and pragmatic solutions encountered during LPDDR6 bring-up.
CXL — Memory Expansion, Pooling, and Beyond Speaker: Minseong Kim
An overview of the evolving CXL memory ecosystem: notable CXL 2.0/3.x features and CMM-DDR5. The session introduces reference software frameworks that enable these capabilities, with practical use cases across direct-attached and pooled memory. We conclude with forward-looking device concepts, architectural trends, and research directions for next-gen CXL memory systems.
PIM — AiM Speaker: Haerang Choi
As the popularity of LLM-based services continues to grow, optimizing inference performance and cost becomes increasingly critical. The efficiency of inference systems, in terms of both performance and cost, is heavily influenced by memory limitations. Traditionally, these memory bottlenecks have been addressed through algorithmic improvements. In this talk, we will introduce SK hynix's ongoing research and development of Processing-in-Memory (PIM) technology, which aims to overcome such limitations by performing computations directly within the memory where data is stored, rather than transferring data back and forth. We will also present the resulting products.
Organizers & Speakers
All affiliations: SK hynix
Haekang Jung — Program Chair
DRAM Development, Vice President
Haekang Jung is a Vice President at SK hynix, where he leads the development of CXL memory modules and infrastructure technologies for DRAM product development. His responsibilities include performance analysis for DRAM-based server systems and RAS solution development based on datacenter operations. He received his Ph.D. from POSTECH in 2011, has authored or co-authored 20+ international technical papers, and holds 40+ U.S. patents.
Kijoon Chang
HBM Product Planning
Kijoon Chang earned his B.S. and M.S. from Yonsei University in 2013, then joined SK hynix as a memory system performance engineer in the DRAM development division. In product planning, he has led pathfinding for innovative memory technologies such as Processing-in-Memory and CXL memory. He is an active member of JEDEC JC42.2 (HBM subcommittee) representing SK hynix. A main contributor to JEDEC HBM4 standards, he is now working with industry partners on next-generation HBM specifications.
Dongha Jung
DRAM Development
Dr. Dongha Jung is a Principal Engineer at SK hynix and an expert in computer architecture and memory systems, with a Ph.D. from Korea University. He has extensive experience in server memory performance and power management, AI memory optimization, and memory security. His work spans detailed analysis of real-world DRAM workloads across system layers, contributions to server memory standardization, and advanced RowHammer mitigation. He currently leads Processing-in-Memory (PIM) R&D efforts.
Jino Choi
DRAM Development,
Jino Choi received his B.S degree in Computer Science from Ajou University in 2020 and joined SK hynix as an Application Engineer. He has been engaged in system-level validation of LPDDR4 and subsequently LPDDR6, and has gained hands-on experience through multiple joint validation projects with leading mobile chipset manufacturers. He is currently responsible for LPDDR6 system-level validation at SK hynix.
Minseong Kim
DRAM Development
Minseong Kim is a Distinguished Engineer at SK hynix specializing in performance analysis of DRAM-based server systems and exploring use cases for emerging memory technologies. His current research focuses on next-generation system architectures and applications involving CXL memory (expansion/pooling) and MRDIMM to enhance data center scalability. He earned a Ph.D. in Electronics, Electrical, and Computer Engineering from Korea University, focusing on system architecture, performance analysis, and prediction.
Wonha Choi
Next Generation Product Planning
Wonha Choi is a Team Leader at SK hynix, specializing in next-generation product planning and enablement. His current research focuses on next-generation system architectures and applications involving CXL memory (expansion/pooling) and MRDIMM to enhance data center scalability.
Haerang Choi
Haerang Choi received the BS and MS degrees from Hanyang University, Seoul, South Korea, in 2005 and 2007, respectively, and the PhD degree in computer science and engineering from Seoul National University, Seoul, South Korea, in 2021. From 2007 to 2016, he designs and develops DRAM circuits in SK hynix. Since 2021, he develops Processing-in/near-memory architecture in SK hynix. His current research interests include memory sub-system and memory-domain architecture for neural network and its accelerator.
JEDEC Policy Compliance Disclaimer
This tutorial is conducted in full compliance with JEDEC policies. We only present information that is already publicly available, enhanced with insights from an SK hynix engineer’s perspective, and do not disclose any other non-public information.