DDR3 SDRAM

Homearrow제품정보arrowComputing MemoryarrowDDR3 SDRAM

H5GQ1H24AFR

The GDDR5 SGRAM is a high speed dynamic random access memory designed for applications requiring high bandwidth.

GDDR5 devices contain the following number of bits:1Gb has 1,073,741,824 bits and sixteen banksThe GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high speed operation.

The device can be configured to operate in x32 mode or x16 (clamshell) mode. The mode is detected during device initialization.

The GDDR5 interface transfers two 32bit wide data words per WCK clock cycle to/from the I/O pins. Corresponding to the 8n prefetch a single write or read access consists of a 256 bit wide, two CKclock cycle data transfer at the internal memory core and eight corresponding 32 bit wide one half WCK clock cycle data transfers at the I/O pins.

The GDDR5 SGRAM operates from a differential clock CK and CK#.

Commands are registered at every rising edge of CK. Addresses are registered at every rising edge of CK and every rising edge of CK#. GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running differential forwarded clock (WCK/WCK#) with both input and output data registered and driven respectively at both edges of the forwarded WCK. Read and write accesses to the GDDR5 SGRAM are burst oriented; an access starts at a selected location and consists of a total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command and the next rising CK# edge are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command and the next rising CK# edge are used to select the bank and the column location for the burst access.

Features

  • Singleendedinterfacefordata,addressandcommand
  • QuarterdataratedifferentialclockinputsCK/CK#forADR/CMD
  • TwohalfdataratedifferentialclockinputsWCK/WCK#,eachassociatedwithtwodatabytes(DQ,DBI#,EDC)
  • DoubleDataRate(DDR)data(WCK)
  • SingleDataRate(SDR)command(CK)
  • DoubleDataRate(DDR)addressing(CK)
  • 16internalbanks
  • 4bankgroupsfortCCDL=3tCK
  • 8nprefetcharchitecture:256bitperarrayreadorwriteaccess
  • Burstlength:8only
  • ProgrammableCASlatency:5to20tCK
  • ProgrammableWRITElatency:1to7tCK
  • WRITEDatamaskfunctionviaaddressbus(single/doublebytemask)
  • Databusinversion(DBI)&addressbusinversion(ABI)
  • Input/outputPLLon/offmode
  • Addresstraining:addressinputmonitoringbyDQpins
  • WCK2CKclocktrainingwithphaseinformationbyEDCpins
  • DatareadandwritetrainingviaREADFIFO
  • READFIFOpatternpreloadbyLDFFcommand
  • DirectwritedataloadtoREADFIFObyWRTRcommand
  • ConsecutivereadofREADFIFObyRDTRcommand
  • Read/Writedatatransmissionintegritysecuredbycyclicredundancycheck(CRC8)
  • READ/WRITEEDCon/offmode
  • ProgrammableEDCholdpatternforCDR
  • ProgrammableCRCREADlatency=0to3tCK
  • ProgrammableCRCWRITElatency=7to14tCK
  • LowPowermodes
  • RDQSmodeonEDCpin
  • Optionalonchiptemperaturesensorwithreadout
  • Auto&selfrefreshmodes
  • Autoprechargeoptionforeachburstaccess
  • 32ms,autorefresh(8kcycles)
  • Temperaturesensorcontrolledselfrefreshrate
  • Ondietermination(ODT);nominalvaluesof60ohmand120ohm
  • Pseudoopendrain(POD15)compatibleoutputs(40ohmpulldown,60ohmpullup)
  • ODTandoutputdrivestrengthautocalibrationwithexternalresistorZQpin(120ohm)
  • Programmableterminationanddriverstrengthoffsets
  • SelectableexternalorinternalVREFfordatainputs;programmableoffsetsforinternalVREF
  • SeparateexternalVREFforaddress/commandinputs
  • VendorID,FIFOdepthandDensityinfofieldsforidentification
  • x32/x16modeconfigurationsetatpowerupwithEDCpin
  • MirrorfunctionwithMFpin
  • BoundaryscanfunctionwithSENpin
  • 1.6V/1.5V+/(3%xVDD)Vsupplyfordeviceoperation(VDD)
  • 1.6V/1.5V+/(3%xVDDQ)VsupplyforI/Ointerface(VDDQ)

Ordering Information


Recently
Viewed
Loading

[Next��]